description2eaf7d782335d406366259661826d6538e
last changeTue, 17 Nov 2009 21:29:25 +0000 (19:29 -0200)
shortlog
2009-11-17 Thiago Borges... Adding file necessary for Logical Synth master
2009-11-17 Thiago Borges... Minimips suporting simulation on RTL Logical Synth
2009-11-17 Thiago Borges... Working RTL version of MiniMIPS
2009-11-17 Thiago Borges... Asynch reset is good!
2009-11-17 Thiago Borges... Testing some modifications to fsm
2009-11-17 Thiago Borges... Dealing with control
2009-11-17 Thiago Borges... Didnt solve
2009-11-17 Thiago Borges... Trying to fix PCEn
2009-11-17 Thiago Borges... Adding ITYPE instruction
2009-11-17 Thiago Borges... Fixed IR order
2009-11-17 Thiago Borges... More missing arguments
2009-11-17 Thiago Borges... Added missing arguments from process
2009-11-17 Thiago Borges... Clearing PCWriteCond
2009-11-17 Thiago Borges... Adding more enabled registers
2009-11-17 Thiago Borges... Adding enabled registers
2009-11-17 Thiago Borges... Enable in datapath
...
heads
6 years ago master